Field of the Invention
The present invention relates to metal oxide based memory devices and methods for manufacturing such devices; and more particularly to memory devices having data storage materials based on metal oxide compounds fabricated with a roughness tuning process including an ion bombardment step of a bottom electrode surface prior to formation of a memory element on the bottom electrode surface. Ion bombardment improves the flatness and decreases the surface roughness of the bottom electrode which is beneficial in achieving a more uniform electrical field during operation, which improves device reliability.
Description of Related Art
Resistive random access memory, RRAM or ReRAM, is a type of nonvolatile memory that provides the benefits of small cell size, scalability, ultrafast operation, low-power operation, high endurance, good retention, large On/Off ratio, and CMOS compatibility. One type of RRAM includes a metal oxide layer than can be caused to change resistance between two or more stable resistance ranges by application of electrical pulses at levels suitable for implementation in integrated circuits, and the resistance can be read and written with random access to indicate stored data.
RRAM memory may include a metal oxide memory element in a current path between first and second electrodes. The electrodes may be terminals to access devices and/or may be coupled to access lines such as bit, word, and source lines. The access lines are connected to circuitry to perform operations, such as SET and RESET operations, which may operate to change the state of the memory element in order to store data.
In prior methods of forming a memory element of an RRAM memory cell, a metal plug, such as a tungsten plug, is deposited using chemical vapor deposition (CVD). A chemical mechanical planarization (CMP) process is performed on the plug. The CMP process is followed by an oxidation process such as rapid thermal oxidation. This oxidation process creates a layer of metal oxide that is the memory element of the RRAM memory cell. The resulting memory cell may have a rough interface between the bottom electrode surface of the tungsten plug formed by the CMP process and the metal oxide memory element. In addition to this rough interface, the rough bottom electrode surface may cause the top surface of the memory element to be rough as well. This roughness of the memory element will cause a rough interface between the memory element and a top electrode deposited on the memory element. These rough interfaces between the electrodes and the memory element lead to a non-uniform oxide profile that may cause severe leakage current, leading to poor switching behavior and poor uniformity, which effect device reliability. Further, the rough interfaces may cause a wide distribution of resistances from cell to cell.
It is therefore desirable to provide a memory cell and method of manufacture that provides interfaces between the memory element and the top and bottom electrodes that have low surface roughness.